Enabling Non-Volatile Memory Technologies

Contact: Onur Mutlu

Existing main memory systems are built using DRAM (dynamic random access memory) storage technology. While DRAM memories can be constructed with high bandwidth and low latency, it is facing significant challenges. First, the demand for main memory capacity and bandwidth is increasing, with the increasing number of cores placed on a single chip, data-intensive applications demanding more data, and the increasing need/trend for consolidation of many applications on a single system in cloud computing, heterogeneous CPU/GPU, and mobile systems. Yet, DRAM capacity is difficult to scale up as we go into the future. Second, power and energy consumption of DRAM-based main memory is becoming a significant concern: DRAM memory consumes power even when idle and needs periodic refresh of data cells as it is volatile. Third, the scaling of DRAM technology to smaller feature sizes is becoming increasingly difficult due to challenges in scaling down the storage element, the capacitor. Scaling of DRAM cells has provided many benefits, including increased storage capacity per unit area, reduced cost, and higher density, which are becoming challenging to obtain. As a result, DRAM alone will likely be inefficient and insufficient in building the main memory hierarchy of future systems. Our goal in this research is to rethink the main memory hierarchy in the presence of the challenges described above and explore the potential of new memory technologies to replace or augment DRAM.

Non-volatile memory/storage (NVM) technologies such as Flash, Phase Change Memory (PCM), and magnetic memory (MRAM) are promising due to their anticipated capacity benefits, non-volatility, and zero idle energy. This project examines the use of NVM technologies as part of main memory, accessed directly using load/store instructions in order to overcome the challenges associated with building a DRAM-only main memory. Unfortunately, these emerging memory technologies have serious shortcomings compared to DRAM, which need to be overcome: 1) they are significantly slower to access, 2) they have very low endurance, 3) they have very high write latency and write energy. Our goal is to redesign the memory hierarchy to overcome these challenges and exploit the new opportunities of NVM technologies. We are rethinking the entire virtual memory design and main memory system to integrate especially Flash and PCM as fundamental main memory components, with the goal of designing a significantly more energy-efficient, cheaper, scalable, high-capacity, and more capable memory/storage system using a hybrid of DRAM, PCM, and Flash memories.



Onur Mutlu


Rachata Ausavarungnirun
Justin Meza
Vivek Seshadri
HanBin Yoon



We thank the members and companies of the PDL Consortium: Alibaba Group, Amazon, Datrium, Facebook, Google, Hewlett Packard Enterprise, Hitachi Ltd., Intel Corporation, IBM, Micron, Microsoft Research, NetApp, Inc., Oracle Corporation, Salesforce, Samsung Semiconductor Inc., Seagate Technology, and Two Sigma for their interest, insights, feedback, and support.




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Last updated 9 October, 2018