Seth Copen Goldstein

www |
GHC 7111
(412) 268-3828
(412) 268-5576
Heather Carney - (412) 268-6737
Mailing Address: Computer Science Department
School of Computer Science
Carnegie Mellon University
5000 Forbes Avenue
Pittsburgh, PA 15213-3891
Associate Professor, SCS and ECE
Electronic Nanotechnology,
Reconfigurable Computing

Research Interests:

My research goal is to develop novel architectures and compilers which will reduce the cost of processors while increasing their performance (operations per second-watt-liter). We are examining how to effectively harness deep-submicron VLSI and electronic nanotechnology to construct architectures which are inexpensive and easy to manufacture and can scale to devices with billions of transistors.

Electronic Nanotechnology. Although we have come to expect, and plan for, the exponential increase in processing power in our everyday lives, today Moore's Law faces imminent challenges both from the physics of deep-submicron CMOS devices and from the enormous costs of next-generation fabrication plants and mask sets. A promising alternative to CMOS-based computing is electronic nanotechnology, which constructs electronic circuits out of nanometer-scale devices that take advantage of quantum-mechanical effects. Our fundamental strategy is to substitute compilation time (which is inexpensive) for manufacturing precision (which is expensive).

Using electronic nanotechnology to build computer systems will require new ways of thinking about computer architecture and compilation. Unlike conventional CMOS, it cannot be used to fabricate construct heterogeneous structures. Instead, one fabricates dense regular (but potentially defective) structures that can be programmed after fabrication to implement complex circuits. We are investigating new circuit families and architectures based on the anticipated manufacturing primitives available for nanoscale devices. We expect the manufacturing process to create devices with defects and are developing diagnostic and compilation methods that can target defective chips with little or no loss in performance. For more information consult NanoFabrics: Spatial Computing Using Molecular Electronics.

Reconfigurable Computing. Reconfigurable computing is a general term that applies to any device which can be configured, at run-time, to implement a function as a hardware circuit. A reconfigurable device has sufficient logic and routing resources that it can be configured, or programmed, to compute a large set of functions in space. Later, it can be re-programmed to perform a different set of functions. It shares attributes of microprocessors, in that it can be programmed post-fabrication, and of custom hardware, in that it can implement a circuit directly. Our investigations are focused on compiler technology and architectures for reconfigurable computing. The architectures are all highly regular and thus can tolerate defects making deep-submicron and electronic nanotechnology manufacture more efficient. Our first architecture, PipeRench, overcomes most of the problems of commercial reconfigurable devices. Our backend compiler is more than two orders of magnitude faster than commercial CAD tools, allowing it to scale to larger devices. Our short-term goal is to bring reconfigurable computing into the mainstream by developing the architectures and compilers necessary to integrate a reconfigurable fabric with a processor core for both high-powered, general-purpose processors and embedded systems.





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Last updated 28 September, 2009