PARALLEL DATA LAB 

PDL Abstract

Extending and Programming the NVMe I/O Determinism Interface for Flash Arrays

ACM Transactions on Storage, Vol. 19, No. 1, Article 5. January 2023.

Huaicheng Li*^, Martin L Putra*, Ronald Shi*, Fadhil I Kurnia‡, Xing Lin†, Jaeyoung Do•, Achmad Imam Kistijantoro˜,
Gregory R Ganger^, Haryadi S Gunawi*

^ Carnegie Mellon University
* University of Chicago
† NetApp
‡ University of Massachusetts Amherst
• Microsoft Research
˜Bandung Institute of Technology

http://www.pdl.cmu.edu/

Predictable latency on flash storage is a long-pursuit goal, yet, unpredictability stays due to the unavoidable disturbance from many well-known SSD internal activities. To combat this issue, the recent NVMe IO Determinism (IOD) interface advocates host-level controls to SSD internal management tasks. While promising, challenges remain on how to exploit it for truly predictable performance.

We present IODA, an I/O deterministic flash array design built on top of small but powerful extensions to the IOD interface for easy deployment. IODA exploits data redundancy in the context of IOD for a strong latency predictability contract. In IODA, SSDs are expected to quickly fail an I/O on purpose to allow predictable I/Os through proactive data reconstruction. In the case of concurrent internal operations, IODA introduces busy remaining time exposure and predictable-latency-window formulation to guarantee predictable data reconstructions. Overall, IODA only adds 5 new fields to the NVMe interface and a small modification in the flash firmware, while keeping most of the complexity in the host OS. Our evaluation shows that IODA improves the 95–99.99th latencies by up to 75×. IODA is also the nearest to the ideal, no disturbance case compared to 7 state-of-the-art preemption, suspension, GC coordination, partitioning, tiny-tail flash controller, prediction, and proactive approaches.

FULL PAPER: pdf