PDL Talk Series
June 25, 2026
TIME: 12:00 noon - 1:00 pm EDT
PLACE: Virtual - a zoom link will be emailed closer to the seminar
SPEAKER: Hugo Sadok, Carnegie Mellon University
A General Device Communication Protocol
Implementing program logic by composing the functionality provided by multiple accelerators, an approach that is now commonly used in ML workloads, is increasingly desirable. However, doing so generally for accelerators is challenging: interconnect protocols, e.g., PCIe and CXL, do not provide all of the mechanisms necessary for arbitrary devices to connect directly; and proprietary protocols, e.g., GPUDirect, that are designed for direct device-to-device communication, assume that at least one of the communicating devices has computation capabilities and memory capacity that are comparable to a CPU. Consequently, directly chaining arbitrary devices, including accelerators, remains out of reach, which imposes performance and efficiency overheads when composing multiple accelerators. In this talk, I will introduce a general Device Communication Protocol (DCP) designed to allow arbitrary pairs of devices to directly communicate with each other. Device heterogeneity posed the main challenge in doing so: devices have significant variance in memory capacity and compute capabilities, and this affects when they can communicate and where data should be stored. DCP develops a general protocol to bridge these gaps and provides three core communication primitives: pass by value, pass by reference, and buffer requests. We show that DCP can closely approximate the performance of specialized interfaces while providing general connectivity inside the host.
BIO: I am a PhD candidate in Computer Science at CMU and a member of the SNAP Lab. My research interests lie at the intersection of computer networks and computer systems. I am grateful to have Prof. Justine Sherry as my advisor and also have the pleasure of working closely with Prof. Aurojit Panda. Before joining CMU, I earned a BS in Electronic and Computer Engineering and an MS in Electrical Engineering, both from UFRJ.
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