PDL Abstract

On-Chip Networks from a Networking Perspective: Congestion and Scalability in Many-core Interconnects

In SIGCOMM 2012, Helsinki, Finland, Aug 2012.

George Nychis, Chris Fallin, Thomas Moscibroda*, Onur Mutlu, Srinivasan Seshan

Carnegie Mellon University
*Microsoft Research Asia


In this paper, we present network-on-chip (NoC) design and contrast it to traditional network design, highlighting similarities and differences between the two. As an initial case study, we examine network congestion in bufferless NoCs. We show that congestion manifests itself differently in a NoC than in traditional networks. Network congestion reduces system throughput in congested workloads for smaller NoCs (16 and 64 nodes), and limits the scalability of larger bufferless NoCs (256 to 4096 nodes) even when traffic has locality (e.g., when an application's required data is mapped nearby to its core in the network). We propose a new source throttlingbased congestion control mechanism with application-level awareness that reduces network congestion to improve system performance. Our mechanism improves system performance by up to 28% (15% on average in congested workloads) in smaller NoCs, achieves linear throughput scaling in NoCs up to 4096 cores (attaining similar performance scalability to a NoC with large buffers), and reduces power consumption by up to 20%. Thus, we show an effective application of a network-level concept, congestion control, to a class of networks – bufferless on-chip networks – that has not been studied before by the networking community.

KEYWORDS: On-chip networks, multi-core, congestion control