PDL Abstract

Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability

ASPLOS2018. The 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems, March 24th – March 28th, Williamsburg, VA, USA.

Maciej Besta1, Syed Minhaj Hassan2, Sudhakar Yalamanchili2, Rachata Ausavarungnirun3,
Onur Mutlu1,3, Torsten Hoefler1

1 ETH Zürich
2 Georgia Institute of Technology
3 Carnegie Mellon University

Emerging chips with hundreds and thousands of cores require networks with unprecedented energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on-chip network design that delivers significant improvements in efficiency and scalability compared to the state-of-the-art. The key idea is to use two concepts from graph and number theory, degree-diameter graphs combined with non-prime finite fields, to enable the smallest number of ports for a given core count. SN is inspired by state-of-the-art off-chip topologies; it identifies and distills their advantages for NoC settings while solving several key issues that lead to significant overheads on-chip. SN provides NoC-specific layouts, which further enhance area/energy efficiency. We show how to augment SN with state-of-the-art router microarchitecture schemes such as Elastic Links, to make the network even more scalable and efficient. Our extensive experimental evaluations show that SN outperforms both traditional low-radix topologies (e.g., meshes and tori) and modern high-radix networks (e.g., various Flattened Butterflies) in area, latency, throughput, and static/dynamic power consumption for both synthetic and real workloads. SN provides a promising direction in scalable and energy-efficient NoC topologies.

KEYWORDS: on-chip-networks; energy efficiency; scalability; manycore systems; parallel processing