PDL Abstract

Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling

Design Automation and Test in Europe (DATE 2013), Mar 19-22, 2013, Grenoble, France.

Yu Cai, Erich F. Haratsch*, Onur Mutlu, Ken Mai

Carnegie Mellon University
5000 Forbes Ave.
Pittsburgh, PA 15213

*LSI Corporation

With continued scaling of NAND flash memory process technology and multiple bits programmed per cell, NAND flash reliability and endurance are degrading. Understanding, characterizing, and modeling the distribution of the threshold voltages across different cells in a modern multi-level cell (MLC) flash memory can enable the design of more effective and efficient error correction mechanisms to combat this degradation. We show the first published experimental measurement-based characterization of the threshold voltage distribution of flash memory. To accomplish this, we develop a testing infrastructure that uses the read retry feature present in some 2Y-nm (i.e., 20-24nm) flash chips. We devise a model of the threshold voltage distributions taking into account program/erase (P/E) cycle effects, analyze the noise in the distributions, and evaluate the accuracy of our model. A key result is that the threshold voltage distribution can be modeled, with more than 95% accuracy, as a Gaussian distribution with additive white noise, which shifts to the right and widens as P/E cycles increase. The novel characterization and models provided in this paper can enable the design of more effective error tolerance mechanisms for future flash memories.