Database Servers on Chip Multiprocessors: Limitations and Opportunities
Proceedings of the 3rd Biennial Conference on Innovative Data Systems Research (CIDR), January 7-10, 2007, Asilomar, California, USA.
Nikos Hardavellas, Ippokratis Pandis, Ryan Johnson, Naju G. Mancheril, Anastassia Ailamaki and Babak Falsafi
School of Computer Science
Electrical and Computer Engineering
Carnegie Mellon University
Pittsburgh, PA 15213
Prior research shows that database system performance is
dominated by off-chip data stalls, resulting in a concerted effort to
bring data into on-chip caches. At the same time, high levels of
integration have enabled the advent of chip multiprocessors and
increasingly large (and slow) on-chip caches. These two trends
pose the imminent technical and research challenge of adapting
high-performance data management software to a shifting
hardware landscape. In this paper we characterize the performance
of a commercial database server running on emerging chip
multiprocessor technologies. We find that the major bottleneck of
current software is data cache stalls, with L2 hit stalls rising from
oblivion to become the dominant execution time component in some cases. We analyze the source of this shift and derive a list of features for future database designs to attain maximum performance.
KEYWORDS: Database Engine. Performance Characterization. Chip Multiprocessors. Staged Database Systems.
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