
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] announcing paper on iSCSI CRCI would like to direct those who are interested in learning more details about the iSCSI CRC process to a paper Luben Tuikov and I wrote and which Julian was kind enough to post on his site at http://www.haifa.il.ibm.com/satran/ips/VinceLubencrc32c.pdf. We intended the paper to be an informational Internet Draft but got lazy when confronted with the daunting task of formatting the equations using only ASCII as required by author guidelines. I summarize some results from the paper below. Notation  The D algorithm divides the message polynomial by the generator polynomial G(x) (33 bits). It performs the classical long division algorithm. The message polynomial must be multiplied by x^32 prior to application of the D algorithm. The SMD algorithm performs simultaneous multiplication by x^32 and division by G(x); so the message polynomial need not be multiplied by x^32 prior to application of the SMD algorithm. That is, the SMD algorithm works on unmodified data to produce results identical to the D algorithm. See point 5 below. The paper derives SMD from D, such that one could implement SMD and get results identical to D, without any data manipulation. The SMD algorithm is also shown in pseudoprogramming language. See point 5 below. The origin of the magic constant 0x1c2d19ed is also shown. Results  The following are equivalent: Using the D algorithm: 1. Initializing CRC register to zeroes. Prefixing the data by 0x2a26f826, multiplying the data polynomial by x^32 and then applying the D algorithm. 2. Initializing CRC register to zeroes. XORing the 32 most significant data bits with 0xFFFFFFFF and multiplying the data polynomial by x^32 and then applying the D algorithm. 3. Initializing CRC register to 0x2a26f826. Multiplying the data polynomial by x^32 and then applying the D algorithm. Using the SMD algorithm: 4. Initializing CRC register to zeroes. Prefixing the data with 0x2a26f826 and applying the SMD algorithm. 5. Initializing CRC register to 0xFFFFFFFF and applying the SMD algorithm. 6. Initializing CRC register to zeroes. XORing the 32 most significant data bits with 0xFFFFFFFF and applying the SMD algorithm. 1, 2 and 5 are directly shown in the paper, as 5 was derived from 2, and 1 from 2. The equivalence of 3, 4 and 6 is implicitly shown, but clearly follows from the definitions used in the paper. Initialization of the CRC register in 1, 2 and 5 is implicit (the D algorithm initializes the register to zero and the SMD algorithm initializes the register to 0xFFFFFFFF). Initialization of the CRC register in 3, 4 and 6 is explicit (an extra step). Vince Cavanna Agilent Technologies
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