RE: ISCSI: found the constant for divide-only circuit!

["CAVANNA,VICENTE V (A-Roseville,ex1)" <vince_cavanna@agilent.com>]

Added iSCSI prefix to subject line.

Actually both "example" and "preferred" seem inappropriate. How about
"reference" or "assumed" implementation? For the claims and examples in the
iSCSI spec to be correct we must refer to an implementation that performs
the following transformations (responses), after n input bits are applied,
on an initial state I(x) and an input M(x):

1. when I(x) is zero, multiplies the input, M(x), by x^32 and divides by
G(x).
2. when M(x) is zero, multiplies the initial state, I(x), by x^n and divides
by G(x).

I have previously provided a serial implementation (the simultaneous
multiply-divide circuit) that performs the above tranformations. Any
parallel implementation properly derived from such a serial implementation
should produce the same transformation and could therefore also be used as
references.

In contrast, the divide-only serial circuit that I have also provided
performs the following transformations on an initial state I(x) and an input
M(x) and iSCSI should not refer to it unless it changed some of its claims
and examples:

1. when I(x) is zero, divides the input, M(x),  by G(x)
2. when M(x) is zero, multiplies the initial state, I(x), by x^n and divides
by G(x)

Note that, by linearity of the CRC circuit, the overall response or
transformation when both I(x) and M(x) are non-zero is the sum of the
individual responses to the input and the initial state.

Vince



-----Original Message-----
From: Paul Koning [mailto:ni1d@arrl.net]
Sent: Friday, December 14, 2001 7:34 AM
To: vince_cavanna@agilent.com
Cc: ips@ece.cmu.edu; ltuikov@yahoo.com; dave_sheehy@agilent.com;
pat_thaler@agilent.com; Julian_Satran@il.ibm.com
Subject: RE: found the constant for divide-only circuit!


Excerpt of message (sent 13 December 2001) by CAVANNA,VICENTE V
(A-Roseville,ex1):
> I have modified the preferred implementation (simultaneous multiply-divide
> circuit) to include the control logic as Paul suggested (similar to
ethernet
> spec). By showing this circuit the iSCSI spec becomes less ambiguous and,
> just maybe, Luben and Paul will be happy men :-).

This is good.

I have one comment: I'd call this an "example" implementation rather
than "preferred".  In fact, it is quite likely not the preferred
implementation if you have to go flying along at several gigabits per
second...  And, since it's an example, I'd put it in some appendix.

There are other example implementations one might point to, for
example the 4 bits at a time table driven approach documented in the
VAX architecture manual, or the 8 bits at a time approach documented
in a paper by Stuart Wecker from sometime before 1980.  I should have
the former somewhere; the latter I don't have but I can probably come
up with a reference to it.

     paul