DATE: Thursday , January 24, 2002
TIME: Noon - 1 pm
PLACE: Hamerschlag Hall, D-Level Conference Room

Sanjay J. Patel

Assistant Professor, Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign

rePLay : A Hardware Framework for Dynamic Optimization

The dynamic behavior of an application speaks volumes about its future behavior. Programs tend to have stable patterns of execution. Microprocessor techniques such as branch prediction, trace caches, and computation reuse attempt to capitalize on these stable patterns in order to reduce a program's running time.

In the same spirit, the rePLay Framework uses a program's dynamic behavior to optimize its instruction stream. The rePLay Framework is a set of microarchitectural features that enable aggressive and safe dynamic optimization of an executing program. rePLay couples mechanisms to identify and optimize repetitive and stable regions of code with a hardware rollback mechanism. The ability to roll back architectural state enables the optimizer to make speculative optimizations without requiring recovery code.

In this talk, I will describe the work done on rePLay by my research group at the University of Illinois (the Advanced Computing Systems Group), including our recent development and performance characterizations of rePLay. I will also describe our work in progress beyond rePLay, including a mechanism that uses rePLay for providing fault-tolerant operation.

Sanjay J. Patel is an Assistant Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. He is a recipient of a 2001 NSF CAREER Award. He received his PhD from the University of Michigan, Ann Arbor in 1999. He is co-author (with Yale N. Patt) of a unique bottom-up introduction to computing titled "Introduction to Computing Systems: from bits and gates to C and beyond." His research interests include processor microarchitecture, computer architecture, and high performance and reliable computer systems. He received a BS and a MS from the University of Michigan and has done hardware verification, logic design, and performance modelling at Digital Equipment Corporation, Intel, and HAL Computer Systems, and has consulted for Transmeta and Jet Propulsion Laboratory.

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