Re: TCP speed

[AndInc@aol.com]

Hi Scott,

Another couple of issues to consider: In an environment like a disk 
controller, the data has to take a few trips:  (1) from MAC to Memory, (2) 
from Memory to Memory (to examine/strip headers), (3) from  Memory to disk.  
Actually, (2) is worse than it looks.  Since most CPUs use a separate CPU 
cache for the DRAM, coherency must be ensured.  The effect of (1) (2) and (3) 
is at least 3xburden, and the side effect of (2) may be much worse than it 
looks.  Also, one must consider that the trips taken in (1) and (3) are not 
just across the memory bus, but across the peripheral bus, which may be much 
lower speed.

The way current disk controllers handle this problem is to pipeline the 
transfer, avoiding the memory trips and cache coherency problems altogether.  
Headers are recognized, stripped and passed to the disk by small hardware 
state machines in Fibre Channel and even ATA.

Is anyone interested in doing a little research, ie, a development of a 
Verilog or VHDL model to show how this could be done for iSCSI?  

I'm interested in this area, and beyond that, it may be to everyone's 
advantage to consider the effects of the protocol on the ability to realize a 
hardware model that could sustain wire rates without a very high performance 
CPU in the path.  I'd suggest using Verilog as the modeling language, and a 
commercial simulation tool like ModelSim to run the simulations.  

Drop me a note if you'd like to participate in an informal bit of group 
research.

Mike Anderson