Seminars

SPECIAL JOINT SDI / INTEL SEMINAR

DATE: Thursday July 19, 2007
TIME: 12:00 pm - 1:00 pm
PLACE: Intel Research Pittsburgh, 4720 Forbes Avenue, CIC Building 4th Floor, Suite 410

NOTE SPECIAL LOCATION

SPEAKER:
Greg Steffan
University of Toronto

TITLE:
A Dynamic x86 Binary-Rewriting Approach to Software Transactional Memory

ABSTRACT:
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing all performance-critical software. Transactional memory (TM) has emerged as a promising programming model allowing programmers to focus on parallelism rather than maintaining correctness and avoiding deadlock. Many implementations of hardware, software, and hybrid support for TM have been proposed; of these, software-only implementations (STMs) are especially compelling since they can be used with current commodity hardware. However, in addition to higher overheads, many existing STM systems are limited to using either certain managed languages or intrusive APIs. Furthermore, transactions in STMs cannot normally contain calls to unobservable code such as shared libraries or system calls. In this paper we present JudoSTM, a novel dynamic x86 binary-rewriting approach to implementing STM that supports C and C++ code and also atomic sections that contain arbitrary calls to shared-libraries. Furthermore, by using value-based conflict-detection JudoSTM additionally supports the transactional execution of both (i) irreversible system calls and (ii) library functions that may contain locks. We significantly lower overheads through several novel optimizations that improve the quality of rewritten x86 code and reduce the cost of conflict detection and write-buffering. We show that our approach performs comparably to Rochester's RSTM library-based implementation---demonstrating that a dynamic binary-rewriting approach to implementing STM is an interesting alternative.

BIO:
Greg Steffan joined the University of Toronto as an Assistant Professor in the Department of Electrical and Computer Engineering in 2002. His area of expertise is in compilers and processor architecture, in particular methods of automatically exploiting parallelism in multicore processors and FPGAs. Greg completed his doctorate at Carnegie Mellon University in 2003, after undergraduate and Masters Degrees at the University of Toronto in 1995 and 1997 respectively. He has also worked in the processor architecture research groups of MIPS Technologies and Compaq Computer Corporation (the VSSAD group, now part of Intel).

For Further Seminar Info:

Host: David O'Hallaron
Visitor Coordinator: Shellee Lank, shellee.j.lank@intel.com

, or visit http://www.pdl.cmu.edu/SDI/