DATE: Thursday, September 18, 2003
TIME: Noon - 1 pm
PLACE: Hamerschlag Hall, D210

Vijay S. Pai
Rice University

Network Interface Architecture and Performance

As local area network links reach ever-growing speeds, Gigabit Ethernet has become a dominant networking mechanism for servers. Although a variety of Gigabit Ethernet network interface cards (NICs) exist to attach PC-based servers to the network, these NICs vary greatly in performance. Even with all other hardware and software configurations unchanged, a network service running on a PC-based server can achieve up to 150% more throughput when using the most effective Gigabit Ethernet NIC as opposed to the least effective one. Analysis through micro-level benchmarks shows that while most tested NICs can send or receive large Ethernet frames at line speed, the NICs vary greatly when processing bidirectional streams of large frames, bidirectional streams of small frames, or unidirectional streams of small frames. Resource contention and per-frame overheads shape the throughput of these traffic patterns and consequently influence the behavior of full-scale applications.

Our research in the Rice Computer Architecture group seeks to address the network interface bottleneck, focusing to date on resource contention. Programmable network interfaces provide opportunities to add functionality beyond standard Ethernet processing, but also lead to overheads relative to application-specific designs. We have developed strategies to parallelize Ethernet processing on multi-CPU network interfaces, allowing programmable interfaces to achieve performance comparable to application-specific designs. Additionally, we have developed a technique called network interface data caching that reduces local interconnect traffic on network servers by caching frequently-requested content on a programmable network interface. Network interface data caching can reduce PCI traffic by up to 57% on a prototype implementation of a uniprocessor web server. This traffic reduction results in up to 31% performance improvement, leading to a peak server throughput of 1571 Mb/s.

Vijay S. Pai received a BSEE degree in 1994, an MS degree in electrical and computer engineering in 1997, and a Ph.D. degree in Electrical and Computer Engineering in 2000, all from Rice University. He joined the faculty of Rice University in September 2001, after a two-year position as a senior developer at iMimic Networking. Vijay's research interests include computer architecture, networking software, and performance evaluation. He was a primary developer and maintainer of the publicly-available Rice Simulator for ILP Multiprocessors (RSIM). Vijay is a member of the Eta Kappa Nu, Phi Beta Kappa, and Tau Beta Pi honorary societies, and his graduate education was partly supported by a Fannie and John Hertz Foundation Fellowship.

Visitor Host :
Babak Falsafi

For Further Seminar Info: