Speaker: Andrew Wolfe, Department of Electrical Engineering, Princeton University
Design Issues for Programmable Video Signal Processor ChipsDate: October 24, 1996
Abstract: Video is the dominant form of widely-distributed information in our society today. The changeover from primarily analog video information to primarily digital information provides vast opportunitues for new forms of information distribution, storage, and management. Key application areas include CD-ROM based multimedia, video teleconferencing, video libraries, on-demand video entertainment, interactive education, and computer vision. These technologies require real-time video signal processing including video compression and decompression, format conversion, video search and database management, feature extraction and image recognition, and interactive image enhancement. Mainstream microprocessors have not been designed to provide these types of computing services, but the technology will soon be available to design a single chip video signal processor with adequate compute power for many of these applications.
The most interesting area of research in video signal processor architecture is the design of programmable VSPs. These will provide opportunities for real-time experimentation with new VSP algorithms and allow for the development of technologically aggressive low-volume VSP applications. An ideal programmable VSP architecture will provide extremely high performance (many GOPS) for VSP applications; be relatively low cost; be easy to program in high-level languages without detailed knowledge of the architecture; and provide predictable, guaranteed, real-time behavior. We believe that given these characteristics, much of the research to date on Instruction Level Parallel architectures and compilers, particularly VLIW and its variations, will provide a strong foundation for initial VSP systems.
Princeton University has initiated a broad-based research effort to develop a viable single-chip VLIW VSP architecture. There are numerous research issues ranging including VLSI design problems, microarchitectural issues, and compilation.
My talk will discuss the design of several key VLSI structures in a .25u process and how they impact architectural decisions. I will discuss the research problems that we intend to address in code generation and I will present early results from some experiments in mapping applications to this architecture.