Summary of T3D / Paragon tutorials and talks at Supercomputing
Date: December 01, 1994
Abstract: There were at least two talks at Supercomputing 94 which might be interesting for people at CMU. In particular, David Bailey et al gave a tutorial on performance tuning for RISC chips (Power2, Alpha, and R8000), which included several non-obvious tweaks to make things go faster on the T3D, and Horst Simon et al gave a talk on the relative performance of OSF/1 vs SUNMOS on the Paragon, why the first run under OSF/1 is always slower than the second, etc. Since we've got people using both these MPPs, I think it would be worthwhile for me to give the guts of both these talks.
Date: October 6, 1994
Abstract: This paper describes the design and implementation in MPI of the parallel vector library CVL, which is used as the basis for implementing nested data-parallel languages such as NESL and Proteus. We outline the features of CVL, and compare the ease of writing and debugging the portable MPI implementation with our experiences writing previous versions in CM-2 Paris, CM-5 CMMD, and PVM 3.0. We give initial performance results for MPI CVL running on the SP-1, Paragon, and CM-5, and compare them with previous versions of CVL running on the CM-2, CM-5, and Cray C90. We discuss the features of MPI that helped and hindered the effort, and make a plea for better support for certain primitives. Finally, we discuss the design limitations of CVL when implemented on current RISC-based MPP architectures, and outline our plans to overcome this by using MPI as a compiler target. CVL and associated languages are available via FTP.