Hardware Assisted Protocol Processing

Network attached storage will be expected to have network bandwidth in excess of 30MB/s. Current processors and busses are easily saturated supporting these loads. The complexity of supporting a network connection can be mitigated by simplifing the network services such that simple hardware assistance mechanism could offload the majority of the work from the drive controller. The reduced protocol stack's functionality is chosen to hardware fast-path the operations common to remote file system access to storage, leaving seldom used cases to software handling. To implement these protocol accelerators, a reconfigurable fabric on a PCI card is used as a rapid prototyping platform to put processing between the host machine and a Fast Ethernet tranceiver. The board implements a full duplex connection with independent send and receive processors which handle all processing at the Ethernet, IP, and UDP protocol levels. The hardware implementation is written in the Verilog hardware design language and is synthesized to the reprogrammable fabric. Speed and complexity measurements are taken directly from the synthesis tools and compared to industry FibreChannel drive controller implementations. In addition, estimates of bandwidth and real system speed are possible using industry controller models.

The PCI Pamette provides a reconfigurable hardware platform on which the prototyping of networking hardward can be easily done. The Pamette board was designed by Digital's Systems Research Center. The Pamette board uses Xilinx 4010E's to provide 40,000 gate-equivalents for prototyping. One Xilinx chip is reserved to provide a PCI bus interface.