NASD: Network Attached Secure Disks
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High-bandwidth, Low-latency, and Scalable Storage Systems
While it is possible to construct off-the-shelf, widely distributed and
massively parallel storage systems with inherent high bandwidth, achieving
low-latency file access remains a significant challenge. We are designing,
implementing, and evaluating scalable, distributed and parallel storage
architectures, interfaces, and protocols to reduce access latency comprehensively.
Our goal is to define the evolutionary path and revolutionary changes
that will enable commodity storage components to be the building blocks
of high-bandwidth, low-latency, secure scalable storage systems.
Our current definition for a NASD device includes all storage systems
that exhibit the following properties: direct client-drive data transfer
in a networked environment, asynchronous oversight by the high level
filesystem, cryptographic support for the integrity of requests, storage
self management opportunities derived from a more abstract and independent
role for storage systems, the ability to extend the feature set of a
NASD for the purpose of applications, as well as for the client operating
system.
This is the World Wide Web home page of the
DARPA/ITO project on "Secure Distributed and Parallel File
Systems Based on Network-Attached Autonomous Disk Drives" which
we have shortened to "Network-Attached Secure Disks (NASD)."
NASD is supported in ITO's
Scalable Systems and Software Services subprogram and carried out
in the School of Computer
Science at Carnegie
Mellon University by the Parallel Data Laboratory,
Garth Gibson, principal investigator.
Please see our section on Work at
CMU for a look at the major NASD Project Components.
Enabling NASD: The Evolution of Drive Electronics
The evolution of drive electronics over the next 5 years directly supports
one of NASD's key enabling technologies -- a powerful on-drive microprocessor
capable of executing the drive's embedded file system, networking and
security code. Driving this evolution is the manufacturers need to reduce
cost by integrating most drive electronics into a single custom ASIC.
This evolution, from multi-chip solutions, such as the 1996 Seagate Barracuda
(shown on the left) to the 1997 Quantum Trident ASIC (middle), allows
drive manufacturers to ride the exponential growth in VLSI technology.
Projecting VLSI-ASIC technology into the future, the entire 1997 Quantum
Trident ASIC (~100,000 gates) will fit into one quarter of a 1999 ASIC
chip (on the right). The remainder of the 1999 ASIC could then be used
to support a 200+ MHz class microprocessor plus hardware support for cryptography
and networking. The integration would reduce drive costs by eliminating
the need for a separate microprocessor (currently available are 30+ MHz
68020 class processors) while providing enough processing cycles for the
ultra-precise servo algorithms necessary to continue the drive's 60% per
year growth in density.
Acknowledgements
We thank the members and companies of the PDL Consortium: American Power Conversion,
Data Domain, Inc.,
EMC Corporation,
Facebook,
Google,
Hewlett-Packard Labs,
Hitachi,
IBM,
Intel Corporation,
LSI,
Microsoft Research,
NetApp, Inc.,
Oracle Corporation,
Seagate Technology,
Sun Microsystems, Symantec Corporation and
VMware, Inc. for
their interest, insights, feedback, and support.
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